Ultra-Low Power Designing for CMOS Sequential Circuits

Abstract

Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold voltages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.

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